A low-power SRAM using bit-line charge-recycling
نویسندگان
چکیده
Permanent magnet and wound rotor synchronous machines (PMSMs and WRSMs) are often used in diesel enginebased portable power generation systems. In these applications, there is a growing desire to improve machine efficiency in order to reduce fossil fuel requirements. In addition, there is a desire to reduce mass to improve mobility. To attempt to address these competing performance objectives, a system analyst is confronted with numerous choices, including machine type (PM or WR), converter architecture (active/passive), and control. Herein, to assist the analyst, design tools capable of performing automated multi-objective optimization of PMSMs and WRSMs connected to both active and passive rectifiers are described. The tools are then used to derive tradeoffs between mass and efficiency for a 3 kW application.
منابع مشابه
A Sub-threshold 9T SRAM Cell with High Write and Read ability with Bit Interleaving Capability
This paper proposes a new sub-threshold low power 9T static random-access memory (SRAM) cell compatible with bit interleaving structure in which the effective sizing adjustment of access transistors in write mode is provided by isolating writing and reading paths. In the proposed cell, we consider a weak inverter to make better write mode operation. Moreover applying boosted word line feature ...
متن کاملA 45 nm 10T Dual-Port SRAM with Shared Bit-Line Scheme for Low Power Operation
This paper proposes a 10T bit-cell of dual-port (DP) SRAM design to improve Static Noise Margin (SNM) and solve write/read disturb issues in nano-scale CMOS technologies. In additional used the row access transistor in the bit-cell, adding Y -access MOS (column-direction access transistor) can improve dummy-read cells’ noise margin and isolate the pre-charge noise from bit-lines in synchronous ...
متن کاملpre-charged bit-lines to ground through the access transistors
This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during read/write operation, only selected cell connected to bit-line whereas, in conventional SRAM (CV-SRAM), all cells in selected row connected to their bit-lines, which in turn develops differential voltages across all bit-lines, and this makes energy consumption o...
متن کاملA Design of Sram Structure for Low Power Using Heterojunction Cmos with Single Bit Line
The Present day workstations, low-power processors, computers and super computers are using fast Static Random Access Memory (SRAMs) and will require, in the future, larger density memories with faster access time and minimum power consumption. Acknowledging the intense requirements for power, in current high performance memories of computing devices, the circuit designers have developed a numb...
متن کاملLow Power 10T SRAM Design for Dynamic Power Reduction
The aim of paper is to get over the problem of 6T SRAM cell where it loses its reliability at low supplies due to degraded noise margins. These is done by using a 10T SRAM where the cell uses a charge sharing technique between the transistors so that SRAM could be made more rigid against the noises that can cause damage to the cell at low power supplies and along with that charge sharing betwee...
متن کاملA Two-Write and Two-Read Multi-Port SRAM with Shared Write Bit-Line Scheme and Selective Read Path for Low Power Operation
This paper proposes a two-write and two-read (2W2R) bit-cell for a multi-port (MP) SRAM design to improve the static noise margin (SNM) and solve the write-disturb issues of nanoscale CMOS technologies. Using an additional Y -access MOS (column-direction access transistor), the 2W2R MP SRAM adopts a scheme of combining the row access transistor and sharing write bit-line with an adjacent bit ce...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2014